The EW Division of Leidos is looking for a FPGA DSP Firmware Design Engineer to work with a multi-disciplined design team (electrical engineers, systems engineers, scientists, etc) to design, develop, simulate, and integrate challenging DSP FPGA designs and RF sensor systems based on given project requirements. Candidate will have a strong background in Digital Signal Processing (DSP) algorithms and their implementation in MATLAB and FPGAs in support of a fast paced, multi-disciplinary design team. This role will also support integration, test, and verification in the final products.
• Analyze, design, simulate, and implement algorithms in hardware descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s).
• Collaborate with a multi-disciplined design team (electrical engineers, systems engineers and scientists) to design and integrate challenging DSP FPGA designs and RF sensor systems.
• Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+, Intel Stratix-10, and Xilinx RFSoC.
• Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
• Perform design constraints generation and verification as well as evaluate synthesis and timing performance reports.
• Implement and validate signal processing concepts such as FFTs, channelizers, digital filters, digital modulation, digital down/up-conversion, adaptive processing, etc. into either new or existing modular HDL designs.
• Analyze, design, simulate, and implement designs which interface to common signaling standards, typical IP hard macros such as SERDES, PLLS, etc. and/or protocols such PCIe, JESD204B, LVDS, etc.
• Analyze schematic diagrams for either custom or commercial-off-the shelf (COTS) electronic hardware involving high-speed digital and/or analog circuitry in associated FPGA-centric systems.
• Develop and maintain requirements documents, functional specification documents, interface control documents, etc.
• Generate and maintain engineering drawings and configuration management policies for FPGA project hierarchy.
• Develop project test plans and test procedures, provide test planning support, and assist in the execution of both lab testing and field testing.
• Provide occasional technical support and/or field support planning, and other field support in general if needed.
• Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications for selecting next-generation components for deliverable systems.
• Work on problems of diverse scope, determining methods and procedures to be used on new assignments, and providing feedback and recommendations to other technical personnel.
• Interact with outside customers, suppliers, and functional peer groups.
• Some travel and work at remote sites for limited time periods may be occasionally required.
• Provide status reports to project managers and/or division production manager as required.
• Must have an active Secret security clearance, TS/SCI level clearance preferred
• Experience with at least one FPGA Integrated Design Environment tool set such as Xilinx Vivado and Mentor Graphics ModelSim.
• Experience in signal processing theory and communications systems and the ability to apply theoretical knowledge in resolving real world problems
• Experience with MATLAB signal processing environment
• BS in Electrical Engineering or Computer Engineering or related degree
• Minimum of 8 years of relevant experience
• MS in Electrical Engineering or Computer Engineering or related
• Experience writing test software in C/C++ or assembly language to validate design
• Experience with hardware integration, test and debug tools (high-speed logic analyzers, scopes, spectrum analyzers, etc.)
• Familiarity with Electronic Warfare applications
• Experience with high-speed (> GHz) design techniques
• ARM or RISC-V embedded processor based SoC design experience
• Experience with performance characteristics of analog data converters, ADCs/DACs.
• Familiarity with JESD204B
• Active TS/SCI level clearance
In order to enter Leidos facilities in the U.S. and to attend Leidos events outside our facilities, employees are required to be vaccinated for COVID-19 or maintain proof of a negative COVID-19 test within 96 hours of entry. In addition, we are receiving guidance from certain customers that onsite contractor personnel will need to be fully vaccinated to access customer facilities. If you are not vaccinated, please consider getting your COVID-19 vaccination as soon as possible. If you have any questions, please contact your Talent Acquisition POC.
Leidos is a Fortune 500® information technology, engineering, and science solutions and services leader working to solve the world’s toughest challenges in the defense, intelligence, civil, and health markets. The company’s 43,000 employees support vital missions for government and commercial customers. Headquartered in Reston, Virginia, Leidos reported annual revenues of approximately $12.30 billion for the fiscal year ended January 1, 2021. For more information, visit www.Leidos.com.
Pay and Benefits
Pay and benefits are fundamental to any career decision. That's why we craft compensation packages that reflect the importance of the work we do for our customers. Employment benefits include competitive compensation, Health and Wellness programs, Income Protection, Paid Leave and Retirement. More details are available here.
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Commitment to Diversity
All qualified applicants will receive consideration for employment without regard to sex, race, ethnicity, age, national origin, citizenship, religion, physical or mental disability, medical condition, genetic information, pregnancy, family structure, marital status, ancestry, domestic partner status, sexual orientation, gender identity or expression, veteran or military status, or any other basis prohibited by law. Leidos will also consider for employment qualified applicants with criminal histories consistent with relevant laws.